TU Wien Informatics

Research Group Parallel Computing

JLT Parallel Computing

[Jesper Larsson Träff, et al.]

Faculty of Informatics (Fakultät für Informatik)
Technical University of Vienna (TU Wien)
Favoritenstrasse 16/184-5 (how to find this)
A-1040 Vienna (Wien)
Austria (Österreich)


The research group for Parallel Computing is a new group (from August 2011) at the Faculty of Informatics under the Institute of Information Systems at the Technical University of Vienna (TU Wien).

The group is concerned with means and methods for efficiently utilizing different, real (e.g., clusters and shared memory systems with accelerators and other HW support, GPUs, experimental highly parallel systems on a chip like the Intel SCC) as well as idealized, (e.g., fully connected communication networks, PRAM) parallel architectures for the solution of given computational problems. This includes the design, development and implementation of parallel algorithms and data structures for fundamental, basic problems (e.g., communication, reduction) and problems incurred by applications, of parallel programming models, interfaces, languages and libraries and their algorithmic support, and the study of parallel architectures.

More concrete themes that will be pursued are:

  1. Parallel programming interfaces for High Performance Computing (HPC) and their efficient algorithmic support and implementation. The Message-Passsing Interface (MPI) is one important paradigm that still poses interesting design and implementation problems, but (combinations with) other programming models are as relevant for addressing architectural features and constraints of current large-scale systems. Some specific topics are quality and performance portability of such interfaces, models for heterogeneous HPC, collective communication algorithms, and hardware offloading and support.
  2. Heterogeneous parallel computing: programming models, interfaces, algorithmic and scheduling support. Effective and efficient general-purpose usage of heterogeneous, parallel architectures (if attainable at all) seems to require adaptivity at many different levels, and this must be provided for in programming and execution models. Some approaches in this direction are being explored in the PEPPHER project. Concrete topics are work-stealing (algorithms and implementations) for socalled mixed-mode parallelism, an extension to classical task-based programming models for integration of strictly parallel tasks, and notions of performance portability.
  3. Parallel algorithms and paradigms for tightly coupled (shared-memory) multiprocessors, and for idealized models of parallel computation. It is a goal to build up solid expertise in parallel algorithms and data structures (also motivated by applications), e.g., in the lock- and wait-free data structure paradigm.
  4. Architectural support for parallel programming models.
If you would like to come and visit us and give a talk, do not hesitate to contact us. We are always open to interesting discussions, problems and collaborations in any of the above outlined areas.

Members of the group

Foundational publications (that is, for the group, in no other sense)

  1. Jesper Larsson Träff, William Gropp, and Rajeev Thakur. Self-consistent MPI performance Guidelines. IEEE Transactions on Parallel and Distributed Systems, 21(5):698-709, 2010.
  2. Jesper Larsson Träff, Andreas Ripke, Christian Siebert, Pavan Balaji, Rajeev Thakur, William Gropp. A pipelined Algorithm for large, irregular all-gather Problems. International Journal of High Performance Computing Applications 24(1):58-68, 2010.
  3. Torsten Hoefler, Rolf Rabenseifner, Hubert Ritzdorf, Bronis R. de Supinski, Rajeev Thakur, Jesper Larsson Träff. The Scalable Process Topology Interface of MPI 2.2. Concurrency and Computation: Practice and Experience, 23: 293-310, 2011.
  4. Peter Sanders, Jochen Speck, Jesper Larsson Träff. Two-tree algorithms for full bandwidth broadcast, reduction and scan. Parallel Computing, 35(12): 581-594, 2009.
  5. Jesper Larsson Träff. Transparent neutral element elimination in MPI reduction operations. In Recent Advances in Message Passing Interface. 17th European MPI Users' Group Meeting, volume 6305, of Lecture Notes in Computer Science, pages 275-284. Springer, 2010.
  6. Jesper Larsson Träff. Compact and Efficient Implementation of the MPI Group Operations. In Recent Advances in Message Passing Interface. 17th European MPI Users' Group Meeting, volume 6305, of Lecture Notes in Computer Science, pages 170-178. Springer, 2010.
  7. Jesper Larsson Träff. A (radical) proposal addressing the non-scalability of the irregular MPI collective interfaces. In 16th International Workshop on High-level Parallel Programming Models and Supportive Environments (HIPS11) at International Parallel and Distributed Processing Symposium (IPDPS), page 42. IEEE Press 2011.
  8. Enes Bajrovic, Jesper Larsson Träff. Using MPI derived datatypes in numerical libraries. In Recent Advances in Message Passing Interface. 18th European MPI Users' Group Meeting, volume, of Lecture Notes in Computer Science, pages. Springer, 2011.
  9. William D. Gropp, Torsten Hoefler, Rajeev Thakur, Jesper Larsson Träff. Performance expectations and guidelines for MPI derived datatypes: a first analysis. In Recent Advances in Message Passing Interface. 18th European MPI Users' Group Meeting, volume, of Lecture Notes in Computer Science, pages. Springer, 2011.

  10. Martin Wimmer, Jesper Larsson Träff. Work-stealing for mixed-mode parallelism by deterministic team-building. In 23rd ACM Symposium on Parallelism in Algorithms and Architectures (SPAA 2011), pages 105-115. ACM Press, 2011.
  11. Martin Wimmer, Jesper Larsson Träff. A work-stealing framework for mixed-mode parallel applications. In Workshop on Multi-threaded Architectures and Applications (MTAAP 2011) at International Parallel and Distributed Processing Symposium (IPDPS 2011), page 48. IEEE Press, 2011.

  12. Siegfried Benkner, Sabri Pllana, Jesper Larsson Träff, Philippas Tsigas, Uwe Dolinsky, Cedric Augonnet, Beverly Bachmayer, Christoph Kessler, David Moloney, Peter Sanders. PEPPHER: Efficient and Productive Usage of Hybrid Computing Systems. IEEE Micro, 2011.
  13. Siegfried Benkner, Sabri Pllana, Jesper Larsson Träff, Philippas Tsigas, Andrew Richards, Raymond Namyst, Beverly Bachmayer, Christoph Kessler, David Moloney, Peter Sanders. The PEPPHER Approach to Programmability and Performance Portability for Heterogeneous many-core Architectures. In Parallel Computing: Current & Future Issues of High-End Computing (ParCo 2011), 2011.

  14. Christoph Kessler, Jörg Keller, Jesper Larsson Träff. Practical PRAM Programming. Wiley, 2001.

Projects

TU Wien Informatics PEPPHER: PErformance Portability and Programmability for HEterogeneous many-core aRchitectures. Our topics include

Guests and visitors

Click here for list of guests and visitors to the group.

Open Positions

The group at the moment has no open positions. Latest PhD position and PostDoc positions had application deadline 30.1.2012 and have been filled: There should regularly be project related positions announced. PLease return.

How to apply (small advice to applicants)

  1. Read the text of the position announcement carefully
  2. Make sure this is a position you are really interested in, and only apply if this is the case. Template applications will in most cases be summarily turned down
  3. Think about a fitting research direction and/or problem that you would like to work in and/or solve, and describe this clearly in at most one page
  4. If necessary, highlight interests, background, and skills in key areas like algorithms and data structures, parallel processing, programming languages/interfaces; briefly, half a page to one page
  5. Send the application to the address and/or persons indicated, with an appropriate, short cover letter
  6. Give one or two references that can be contacted for supplementary information
  7. Include proof of relevant degrees and/or qualifications

Teaching

The group will regularly offer courses in the following topics (click here for general description)

Hardware

AMD 48-core shared-memory node. AMD based 36-node InfiniBand cluster with 576 cores.